Wafer Acceptance Testing (WAT), also known as Parametric Test, E-Test, or Process Control Monitor (PCM), is the cornerstone of semiconductor manufacturing, ensuring that wafers meet the highest standards of quality, reliability, and performance. By designing specialized test structures on the wafer (usually along the dicing line), WAT can optimize quality control in the manufacturing process, helping fabs improve yield, reduce costs, and accelerate the market introduction of cutting-edge technologies. With the continuous development of the semiconductor industry, WAT plays a key role in new process R&D, process monitoring and production maintenance, new product introduction, and reliability engineering.
Introduction
As a key component of semiconductor manufacturing process control, the development of wafer acceptance test (WAT) technology dates back to 1978. As an industry pioneer, TSMC was the first to make a breakthrough in this field by successfully applying for a patent for "Automated Wafer Acceptance Test Method". With the continuous evolution of semiconductor manufacturing processes, TSMC further obtained the patent for "Integrated Defect Yield Management and Query System" in 1997, marking a new stage of development in the application of WAT technology in semiconductor manufacturing process control.
1.1 Typical Key Parameters and Test Structures
The standardized implementation of WAT (Wafer Acceptance Test) is to embed a special test structure on a wafer to perform non-destructive measurements. WAT testing focuses on the devices in a specific Test Structure of a wafer to measure and acquire their electrical and physical parameters to ensure that the wafer meets the design specifications and process requirements. The test structure is sometimes called Test Key, Test Element Group (TEG) and so on. Typical devices to be tested in a test structure include:
Resistance / Resistors:
Used to measure sheet resistance and contact resistance.
Capacitance / Capacitors:
Designed to evaluate capacitance and dielectric integrity.
Leakage Current / Diodes:
Used to assess junction properties and leakage current.
Ids (Drain-to-Source Current) / Transistors:
Provide data on key transistor parameters such as Ids current, threshold voltage, and gate oxide integrity.
Depending on the different stages of process development or mass production, the number of test structures and devices to be tested on the wafer may vary. For example, in TD R&D, each Reticle on the wafer is often filled with test structures; while in mass production, the test structures are designed to be located at the scribe line between the product Die and are evenly distributed at different locations (e.g., the center and 5 points up and down on the left, right and right sides) to help identify spatial variations in the manufacturing process.
Each die on the reticle is covered with WAT test structures
The WAT test structure is distributed on the dashed path between the Die and the Die
WAT data must distinguish between local variations and global variations. By analyzing these variations, manufacturers can identify the root causes of defects and assess whether they are limited to a specific region or indicate a systemic problem. This distinction is essential for implementing targeted process optimization and maintaining consistency throughout the production line.
* Local variations
Local variations refer to differences within a single die or small regions of the wafer. These can arise from lithography or etching inconsistencies.
Local variations are particularly critical in advanced technologies, where even minor deviations can significantly impact device performance.
* Global Variations
Global Variations refer to differences at wafer-to-wafer or lot-to-lot data. These can identify equipment drift or process instability.
2. Importance of WAT
As one of the core tools for semiconductor manufacturing process control, WAT test has always maintained its irreplaceable importance, playing a key role in ensuring chip yield and improving process stability.
WAT testing enables the acquisition of data to monitor and verify the stability of the manufacturing process, making it an important part of the process control monitoring (PCM) system to support production quality improvement. WAT data is generated by the wafer fabrication facility (FAB) at the end of the manufacturing process as an initial measurement of the wafer, designed to confirm its structural integrity during the manufacturing process. While evaluating and analyzing PCM is challenging due to the limited amount of data, WAT data is an important tool for predicting possible problems or failures in subsequent processes. As such, WAT is not only a PCM tool in production, but also one of the most important tools available to engineers in the new product development process. A wide range of engineered WAT test structures can help to identify failures and problems that affect yield and operational inefficiencies.
Typically, Fabless (fabless customers) have access to production WAT data for each wafer shipped, which is critical to ensure consistency in the semiconductor manufacturing process, aiming to avoid significant revenue loss due to poor yields.
Wafer map with locations of WAT devices to be tested
3.WAT test method
3.1 WAT Tester
WAT testing requires the use of a variety of different test resources to make measurements in areas such as current and voltage (IV) and capacitance and voltage (CV). These test resources or instruments typically include source/measurement units (SMUs), precision digital voltmeters (DMMs), pulse generators (PGUs), and capacitance meters (LCRs). All test resources are connected to the test points of each test structure on the wafer through a switching matrix (low voltage, low leakage switching matrix, or high voltage switching matrix for power semiconductors), where a probe card is used to make contact with the probes and complete the electrical test of the device to be tested (MOSFET, resistor, capacitor, etc.). The above test resources and instruments are managed and controlled by the WAT test system software, which, in combination with test heads, structural components and other components, together form a complete WAT test system.
The following figure shows the schematic diagram of Semight high voltage WAT test system.
Schematic diagram of WAT tester
The first is the low-current measurement, which requires a longer stabilization time due to the capacitive effect of the cable insulation. Especially if the voltage needs to be scanned during the test, this parasitic capacitance triggers charging currents, which affects the measurement accuracy.
Second, with the wide application of wide bandgap devices such as Silicon Carbide (SiC), new requirements have been placed on test equipment, including the need for new types of test resources such as high-voltage SMUs and high-voltage switching matrices.
Finally, advanced processes will require new types of test structures, such as Array Test, to arrange a large number of devices to be tested to obtain various parameter data and gain insight into the local differences of Intra-Reticle. Traditional serial WAT testers will not be able to meet the needs of Array Test due to their outdated architecture and low-test efficiency. The industry is in need of parallel WAT testers with new test methods and high efficiency.
Array Test Structures
WAT (Wafer Acceptance Test) is a crucial process control monitoring (PCM) tool in the wafer manufacturing process and plays a decisive role in semiconductor product quality and yield. It provides local (wafer-specific) and global (wafer-to-lot or lot-to-lot) statistics that provide critical support for manufacturing process optimization.
Future directions will focus on more complex test array designs and parallel test capability enhancements to further reduce test time and cost.
