CPO, Co-Packaged Optics, Nexustest

I. Introduction & Industry Background

Driven by the exponential surge in computing demand, Co-Packaged Optics (CPO) has emerged as a focal point in data center architecture and advanced packaging. The global CPO market is projected to experience a compound annual growth rate (CAGR) of 137% between 2024 and 2030.

Because CPO systems are highly integrated and intrinsically non-reworkable, even minor component defects can result in the catastrophic scrapping of the expensive GPUs or ASICs co-packaged with them. Consequently, enforcing rigorous Known Good Die (KGD) testing prior to final packaging is of paramount importance:
Yield Assurance: Guaranteeing that only fully validated, defect-free dies are integrated into the system ecosystem.

Cost Optimization: Screening out defective components at the front-end to prevent exorbitant packaging costs and catastrophic assembly yield losses.

II. Typical CPO Test Insertions

The CPO manufacturing, assembly, and test flow typically encompasses four critical test insertions:

1. PIC Wafer Sort: Conducting optical Wafer Acceptance Testing (WAT) to perform initial screening for Photonic Integrated Circuit (PIC) KGDs.

2. Advanced Packaging (AP) & Optical Engine (OE) Wafer Sort: Following the co-packaging of Electronic Integrated Circuits (EIC) and PICs, DC and interconnectivity testing are executed for process validation and qualification.
3. Singulation, Placement & OE Die-Level Testing (OE DLT): Representing a major industry bottleneck. Post-wafer singulation and receptacle attachment, comprehensive at-speed functional testing is performed to yield validated OE KGDs.
4. CPO Module-Level System Testing: Executing system-level functional and comprehensive performance validation after final module assembly.
III. Nexustest HVM Solution: OPB8201 + SP9000e
To address the critical requirements of High-Volume Manufacturing (HVM), Nexustest has introduced a fully integrated, high-speed Optical Engine Die-Level KGD test solution:

OPB8201: Optical Engine Die-Level KGD Handler

Supports singulated die testing with integrated receptacles.
Seamlessly compatible with standard optical connectors and Fiber Arrays (FAUs).
Delivers sub-micron precision with a system alignment accuracy of ≤±10 μm.
Features test sockets engineered with air-damping technology and a dual contact-force mechanism.
Empowers high throughput with a quad-site (4-site) parallel testing architecture, achieving a Units Per Hour (UPH) rate of approximately 400.

SP9000e: Optical Engine Tester

Utilizes a Tester-on-DUT-Board architecture to dramatically minimize signal path degradation.
The mainframe integrates 65 GHz optical instrumentation and 224 Gbps BERT (Bit Error Rate Tester) cards.
A single tester seamlessly drives all 4 parallel test sites.
IV. DoE Data & Signal Integrity Validation Results
To validate the engineering feasibility and performance superiority of this HVM solution, our R&D teams gathered comprehensive Design of Experiments (DoE) and high-speed microwave Signal Integrity (SI) data in real-world production environments:

1. High Parallelism & Precision Thermal Control

Throughput (UPH): With a per-die test time of ≤30 seconds, the quad-site architecture sustains a stable UPH of 400, significantly outperforming legacy single- or dual-site configurations in production efficiency.
Active Temperature Control (ATC): Engineered with transient power compensation, the system actively regulates and sustains target test temperatures during intensive at-speed operations.

2. Signal Integrity & Eye Diagram Metrics

Low-Loss Microwave Interconnects: Demonstrates insertion losses of -7.17 dB at 28 GHz and -13.13 dB at 56 GHz. Impedance continuity strictly meets the stringent tolerances required for 112 Gbps PAM4 and emerging 224 Gbps node specifications.

High-Fidelity Eye Diagrams & Low TDECQ: Operating at 112 Gbps PAM4, the core optical penalty metric—TDECQ—registers at an impressive 0.84 dB using PRBS16, and as low as 0.44 dB with SSPRQ patterns, ensuring highly accurate characterization of the optical engine's true physical-layer performance.
V. Summary & Outlook
Optical Engine Die-Level Testing (DLT) effectively enables robust KGD validation at-speed and across multi-temperature domains. The synergistic integration of the OPB8201 handler and the SP9000e tester establishes a mature, production-ready HVM solution, currently supporting parallel testing at data rates up to 112 Gbps.
Looking ahead to future technological roadmaps, Nexustest is aggressively advancing its 224 Gbps data rate test capabilities. Core developmental priorities include the continuous optimization of PCB routing topologies and the integration of ultra-high-bandwidth RF connectors.